Clock jitter is a measure of the non periodic reality of a practical clock, i.e. the rising edge of a typical square wave clock will not always arrive at a given destination exactly one period later, it may arrive slightly before or after and it is this difference in the period which is known as clock jitter.
The beautiful ASCII art shown above illustrates what clock jitter is, it is represented by the red regions before and after all of the edges indicating that each edge will occur somewhere within that region.
An ideal clock has no jitter, the rising edge always occurs exactly one period in time later. In the picture above it is the blue square wave, but unfortunately in practice this is not what we will observe.
What is it caused by?
Clock jitter is caused by many factors, to name just a few the clock generator circuit itself will have various noise sources as well as parasitic elements (distributed capacitance, inductance and resistance), interference from nearby circuitry, power supply variability as well as the physical placement of the clock from the destinations which in the context of an FPGA for example could be the clock inputs of thousands of flip flops. Furthermore for FPGA's clock jitter directly impacts both the setup and hold times, we maintain a setup and hold time to ensure we have enough time to capture the edge to avoid the dreaded metastable state of a flip flop.
How is it measured?
Let's take a phase-locked loop, PLL as an example. The jitter in a PLL consists of two components a random component, due to primarily thermal noise sources throughout the system and a deterministic component due to power supply noise as well as other noise sources.
As for all signals we can view them in both the time and frequency domains.
For the time domain we can measure the jitter with a low noise floor oscilloscope where we measure the deviation of the zero crossing compared with an ideal clock (no jitter). We take at least 1000 samples of this difference to then compute the mean, standard deviation and peak to peak values given the jitter is random in nature.
For the frequency domain we can use a spectrum analyzer where we mix the jittery clock of interest with a reference clock, and then observe the resultant spectrum after additional filtering. The spectrum of an ideal clock would consist of just a single peak at the fundamental frequency, however, a real signal will have additional peaks due to the non-linearities and harmonics.
How can we handle it in digital systems?
For digital systems, it is the data delay from one flip-flop to the receiving flip-flop that is of concern and whether it can tolerate a clock time period made lower by jitter. To combat this we first need to be aware of it, and if the system is operating at a high frequency for the system we can use techniques such as pipelining to ease the timing pressure between flip flops.
We will take a deep dive look at various techniques of implementing very high speed digital systems as part of the FPGA's and Digital Signal Processing Course.